ST7232AJ2 datasheet(101/157 Pages) STMICROELECTRONICS

101 / 157 page

ST7232A

101/157

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

EXTENDED RECEIVE PRESCALER DIVISION

Read/Write

Reset Value: 0000 0000 (00h)

Allows setting of the Extended Prescaler rate divi-

sion factor for the receive circuit.

Bits 7:0 = ERPR[7:0] 8-bit Extended Receive

Prescaler Register.

The extended Baud Rate Generator is activated

when a value different from 00h is stored in this

from the 16 divider (see Figure 53) is divided by

the binary factor set in the SCIERPR register (in

the range 1 to 255).

The extended baud rate generator is not used af-

ter a reset.

EXTENDED TRANSMIT PRESCALER DIVISION

Read/Write

Reset Value:0000 0000 (00h)

Allows setting of the External Prescaler rate divi-

sion factor for the transmit circuit.

Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit

Prescaler Register.

The extended Baud Rate Generator is activated

when a value different from 00h is stored in this

from the 16 divider (see Figure 53) is divided by

the binary factor set in the SCIETPR register (in

the range 1 to 255).

The extended baud rate generator is not used af-

ter a reset.

Table 21. Baudrate Selection

ERPR

ETPR

Symbol

Parameter

Conditions

Standard

Baud

Rate

Unit

fCPU

Accuracy

vs. Standard

Prescaler

fTx

fRx

Communication frequency

8MHz

~0.16%

Conventional Mode

TR (or RR)=128, PR=13

TR (or RR)= 32, PR=13

TR (or RR)= 16, PR=13

TR (or RR)= 8, PR=13

TR (or RR)= 4, PR=13

TR (or RR)= 16, PR= 3

TR (or RR)= 2, PR=13

TR (or RR)= 1, PR=13

300

1200

2400

4800

9600

10400

19200

38400

~300.48

~1201.92

~2403.84

~4807.69

~9615.38

~10416.67

~19230.77

~38461.54

~0.79%

Extended Mode

ETPR (or ERPR) = 35,

TR (or RR)= 1, PR=1

14400 ~14285.71

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