IO107PDB1 datasheet(116/210 Pages) MICROSEMI

116 / 210 page

Pin Descriptions

3- 4

R ev isio n 1 5

In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In

such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA

pin.

Note that to operate at all VJTAG voltages, 500

Ω to 1 kΩ will satisfy the requirements.

Special Function Pins

No Connect

This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be

left floating with no effect on the operation of the device.

Do Not Connect

This pin should not be connected to any signals on the PCB. These pins should be left unconnected.

Related Documents

User’s Guides

ProASIC FPGA Fabric User’s Guide

http://www.microsemi.com/soc/documents/PA3_UG.pdf

Packaging

The following documents provide packaging information and device selection for low power flash

devices.

Product Catalog

http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf

Lists devices currently recommended for new designs and the packages available for each member of

the family. Use this document or the datasheet tables to determine the best package for your design, and

which package drawing to use.

Package Mechanical Drawings

http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf

This document contains the package mechanical drawings for all packages currently or previously

supplied by Actel. Use the bookmarks to navigate to the package mechanical drawings.

Additional packaging materials are at http://www.microsemi.com/products/solutions/package/docs.aspx.

IO107PDB1 датащи(PDF) 116 Page - Microsemi Corporation