IO107PDB1 datasheet(108/210 Pages) MICROSEMI

номер детали	IO107PDB1

подробное описание детали	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

PDF	210 Pages

Scroll/Zoom	100%

производитель	MICROSEMI [Microsemi Corporation]

домашняя страница	http://www.microsemi.com

Logo

108 / 210 page

ProASIC3 Flash Family FPGAs

Re vi s i on 15

2 - 103

Table 2-120 • A3P250 FIFO 512×8

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter

Description

–2

–1

Std.

Units

tENS

REN, WEN Setup Time

3.75

4.27

5.02

tENH

REN, WEN Hold Time

0.00

tBKS

BLK Setup Time

0.19

0.22

0.26

tBKH

BLK Hold Time

0.00

tDS

Input Data (WD) Setup Time

0.18

0.21

0.25

tDH

Input Data (WD) Hold Time

0.00

tCKQ1

Clock High to New Data Valid on RD (flow-through)

2.17

2.47

2.90

tCKQ2

Clock High to New Data Valid on RD (pipelined)

0.94

1.07

1.26

tRCKEF

RCLK High to Empty Flag Valid

1.72

1.96

2.30

tWCKFF

WCLK High to Full Flag Valid

1.63

1.86

2.18

tCKAF

Clock High to Almost Empty/Full Flag Valid

6.19

7.05

8.29

tRSTFG

RESET Low to Empty/Full Flag Valid

1.69

1.93

2.27

tRSTAF

RESET Low to Almost Empty/Full Flag Valid

6.13

6.98

8.20

tRSTBQ

RESET Low to Data Out Low on RD (flow-through)

0.92

1.05

1.23

RESET Low to Data Out Low on RD (pipelined)

0.92

1.05

1.23

tREMRSTB

RESET Removal

0.29

0.33

0.38

tRECRSTB

RESET Recovery

1.50

1.71

2.01

tMPWRSTB

RESET Minimum Pulse Width

0.21

0.24

0.29

tCYC

Clock Cycle Time

3.23

3.68

4.32

FMAX

Maximum Frequency for FIFO

310

272

231

MHz

IO107PDB1 датащи(PDF) 108 Page - Microsemi Corporation

IO107PDB1 датащи(HTML) 108 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL