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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IO96NDB2V1 датащи(PDF) 162 Page - Microsemi Corporation |
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IO96NDB2V1 датащи(HTML) 162 Page - Microsemi Corporation |
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162 / 242 page  ProASIC3L DC and Switching Characteristics 2-146 Revision 13 Timing Characteristics Table 2-218 • FIFO – Applies to 1.5 V DC Core Voltage Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –1 Std. Units tENS REN, WEN Setup Time 1.40 1.65 ns tENH REN, WEN Hold Time 0.02 0.02 ns tBKS BLK Setup Time 0.40 0.47 ns tBKH BLK Hold Time 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.19 0.22 ns tDH Input Data (WD) Hold Time 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.40 2.83 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.91 1.07 ns tRCKEF RCLK High to Empty Flag Valid 1.75 2.06 ns tWCKFF WCLK High to Full Flag Valid 1.66 1.96 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.31 7.42 ns tRSTFG RESET Low to Empty/Full Flag Valid 1.73 2.03 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.25 7.35 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.94 1.11 ns RESET Low to Data Out Low on RD (pipelined) 0.94 1.11 ns tREMRSTB RESET Removal 0.29 0.34 ns tRECRSTB RESET Recovery 1.53 1.80 ns tMPWRSTB RESET Minimum Pulse Width 0.55 0.64 ns tCYC Clock Cycle Time 5.10 5.87 ns FMAX Maximum Frequency for FIFO 196 170 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. |
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