IO96NDB2V1 datasheet(155/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

2-139

Table 2-215 • RAM4K9 – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V

Parameter

Description

–1

Std. Units

tAS

Address setup time

0.33 0.39

tAH

Address hold time

0.00 0.00

tENS

REN, WEN setup time

0.19 0.22

tENH

REN, WEN hold time

0.13 0.15

tBKS

BLK setup time

0.31 0.36

tBKH

BLK hold time

0.02 0.03

tDS

Input data (DIN) setup time

0.24 0.29

tDH

Input data (DIN) hold time

0.00 0.00

tCKQ1

Clock High to new data valid on DOUT (output retained, WMODE = 0)

2.38 2.80

Clock High to new data valid on DOUT (flow-through, WMODE = 1)

3.14 3.69

tCKQ2

Clock High to new data valid on DOUT (pipelined)

1.19 1.40

tC2CWWL1

Address collision clk-to-clk delay for reliable write after write on same address –

applicable to closing edge

0.25 0.30

tC2CRWH1

Address collision clk-to-clk delay for reliable read access after write on same

address – applicable to opening edge

0.27 0.32

tC2CWRH1

Address collision clk-to-clk delay for reliable write access after read on same

address – applicable to opening edge

0.37 0.44

tRSTBQ

RESET Low to data out Low on DOUT (flow-through)

1.23 1.45

RESET Low to data out Low on DOUT (pipelined)

1.23 1.45

tREMRSTB

RESET removal

0.38 0.45

tRECRSTB

RESET recovery

2.00 2.35

tMPWRSTB RESET minimum pulse width

0.63 0.72

tCYC

Clock cycle time

5.75 6.61

FMAX

Maximum frequency

174 151 MHz

Notes:

1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

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