64GA106 datasheet(115/330 Pages) MICROCHIP

115 / 330 page

 2010 Microchip Technology Inc.

DS39905E-page 115

PIC24FJ256GA110 FAMILY

8.0

OSCILLATOR

CONFIGURATION

The oscillator system for PIC24FJ256GA110 family

devices has the following features:

• A total of four external and internal oscillator options

as clock sources, providing 11 different clock modes

• On-chip 4x PLL to boost internal operating frequency

on select internal and external oscillator sources

• Software-controllable switching between various

clock sources

• Software-controllable postscaler for selective

clocking of CPU for system power savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and permits safe application recovery

or shutdown

• A separate and independently configurable system

clock output for synchronizing external hardware

A simplified diagram of the oscillator system is shown

in Figure 8-1.

FIGURE 8-1:

PIC24FJ256GA110 FAMILY CLOCK DIAGRAM

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F

Family

Reference

Manual”

Section 6. “Oscillator”

(DS39700).

Secondary Oscillator

SOSCEN

Enable

Oscillator

SOSCO

SOSCI

Clock Source Option

for Other Modules

OSCI

OSCO

Primary Oscillator

XT, HS, EC

CLKDIV<10:8>

WDT, PWRT

8 MHz

FRCDIV

31 kHz (nominal)

FRC

Oscillator

LPRC

Oscillator

SOSC

LPRC

Clock Control Logic

Fail-Safe

Clock

Monitor

FRC

(nominal)

4 x PLL

XTPLL, HSPLL

ECPLL,FRCPLL

8 MHz

4 MHz

CPU

Peripherals

CLKDIV<14:12>

CLKO

Reference Clock

Generator

REFO

REFOCON<15:8>

DIV/2

(FCY)

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