64GA106 datasheet(253/330 Pages) MICROCHIP

253 / 330 page

 2010 Microchip Technology Inc.

DS39905E-page 253

PIC24FJ256GA110 FAMILY

25.3.1

WINDOWED OPERATION

The Watchdog Timer has an optional Fixed Window

mode of operation. In this Windowed mode, CLRWDT

instructions can only reset the WDT during the last 1/4

of the programmed WDT period. A CLRWDT instruction

executed before that window causes a WDT Reset,

similar to a WDT time-out.

Windowed WDT mode is enabled by programming the

WINDIS Configuration bit (CW1<6>) to ‘0’.

25.3.2

CONTROL REGISTER

The WDT is enabled or disabled by the FWDTEN

Configuration bit. When the FWDTEN Configuration bit

is set, the WDT is always enabled.

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN

control bit is cleared on any device Reset. The software

WDT option allows the user to enable the WDT for

critical code segments and disable the WDT during

non-critical segments for maximum power savings.

FIGURE 25-2:

WDT BLOCK DIAGRAM

25.4

Program Verification and

Code Protection

PIC24FJ256GA110

family

devices

provide

two

complimentary methods to protect application code

from overwrites and erasures. These also help to

protect the device from inadvertent configuration

changes during run time.

25.4.1

GENERAL SEGMENT PROTECTION

For all devices in the PIC24FJ256GA110 family, the

on-chip program memory space is treated as a single

block, known as the General Segment (GS). Code

protection for this block is controlled by one Configura-

tion bit, GCP. This bit inhibits external reads and writes

to the program memory space. It has no direct effect in

normal execution mode.

Write protection is controlled by the GWRP bit in the

Configuration Word. When GWRP is programmed to

‘0’, internal write and erase operations to program

memory are blocked.

LPRC Input

WDT Overflow

Wake from Sleep

31 kHz

Prescaler

Postscaler

FWPSA

SWDTEN

FWDTEN

Reset

All Device Resets

Sleep or Idle Mode

LPRC Control

CLRWDT

Instr.

PWRSAV

Instr.

(5-bit/7-bit)

1:1 to 1:32.768

WDTPS<3:0>

1 ms/4 ms

Exit Sleep or

Idle Mode

WDT

Counter

Transition to

New Clock Source

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