64GA106 datasheet(230/330 Pages) MICROCHIP

230 / 330 page

PIC24FJ256GA110 FAMILY

DS39905E-page 230

 2010 Microchip Technology Inc.

AD1CHS: A/D INPUT SELECT REGISTER

R/W-0

U-0

R/W-0

CH0NB

—

CH0SB4(1)

CH0SB3(1)

CH0SB2(1)

CH0SB1(1)

CH0SB0(1)

bit 15

bit 8

R/W-0

U-0

R/W-0

CH0NA

—

CH0SA4

CH0SA3

CH0SA2

CH0SA1

CH0SA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

CH0NB:

Channel 0 Negative Input Select for MUX B Multiplexer Setting bit

= Channel 0 negative input is AN1

= Channel 0 negative input is VR-

bit 14-13

Unimplemented:

Read as ‘0’

bit 12-8

CH0SB<4:0>:

Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1)

10001

= Channel 0 positive input is internal band gap reference (VBG)

10000

= Channel 0 positive input is VBG/2

01111

= Channel 0 positive input is AN15

01110

= Channel 0 positive input is AN14

01101

= Channel 0 positive input is AN13

01100

= Channel 0 positive input is AN12

01011

= Channel 0 positive input is AN11

01010

= Channel 0 positive input is AN10

01001

= Channel 0 positive input is AN9

01000

= Channel 0 positive input is AN8

00111

= Channel 0 positive input is AN7

00110

= Channel 0 positive input is AN6

00101

= Channel 0 positive input is AN5

00100

= Channel 0 positive input is AN4

00011

= Channel 0 positive input is AN3

00010

= Channel 0 positive input is AN2

00001

= Channel 0 positive input is AN1

00000

= Channel 0 positive input is AN0

bit 7

CH0NA:

Channel 0 Negative Input Select for MUX A Multiplexer Setting bit

= Channel 0 negative input is AN1

= Channel 0 negative input is VR-

bit 6-5

Unimplemented:

Read as ‘0’

bit 4-0

CH0SA<4:0>:

Channel 0 Positive Input Select for MUX A Multiplexer Setting bits

Implemented combinations are identical to those for CHOSB<4:0> (above).

Note 1:

Combinations, ‘10010’ through ‘11111’, are unimplemented; do not use.

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