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SPC5644AF0MLU3 датащи(PDF) 110 Page - Freescale Semiconductor, Inc |
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SPC5644AF0MLU3 датащи(HTML) 110 Page - Freescale Semiconductor, Inc |
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110 / 138 page ![]() MPC5644A Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 110 3.17.5 External interrupt timing (IRQ pin) Figure 22. External Interrupt Timing 3.17.6 eTPU timing Table 44. External interrupt timing1 1 IRQ timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA =TL to TH. # Characteristic Symbol Min Max Unit 1 IRQ Pulse Width Low tIPWL 3— tcyc 2 IRQ Pulse Width High tIPWH 3— tcyc 3 IRQ Edge to Edge Time2 2 Applies when IRQ pins are configured for rising edge or falling edge events, but not both. tICYC 6— tcyc Table 45. eTPU timing1 1 eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA =TL to TH, and CL = 200 pF with SRC = 0b00. # Characteristic Symbol Min Max Unit 1 eTPU Input Channel Pulse Width tICPW 4— tcyc 2 eTPU Output Channel Pulse Width tOCPW 22 2 This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). —tcyc IRQ 1 2 3 |
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