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STM32F217VG датащи(PDF) 138 Page - STMicroelectronics

номер детали STM32F217VG
подробное описание детали  ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/1284KB RAM
PDF  175 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STM32F217VG датащи(HTML) 138 Page - STMicroelectronics

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Electrical characteristics
STM32F21xxx
138/175
DocID17050 Rev 9
Figure 61. Synchronous non-multiplexed PSRAM write timings
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Table 78. Synchronous non-multiplexed PSRAM write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
2THCLK- 1
-
ns
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)
-
1
ns
td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)
1
-
ns
td(CLKL-
NADVL)
FSMC_CLK low to FSMC_NADV low
-
5
ns
td(CLKL-
NADVH)
FSMC_CLK low to FSMC_NADV high
6
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25)
8
-
ns
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
-
1
ns
td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high
1
-
ns
FSMC_CLK
FSMC_NEx
FSMC_A[25:0]
FSMC_NWE
FSMC_D[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tw(CLK)
tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-AV)
td(CLKL-AIV)
td(CLKL-NWEH)
td(CLKL-NWEL)
td(CLKL-Data)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
ai14993g
FSMC_NADV
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-Data)
FSMC_NBL
td(CLKL-NBLH)



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