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PIC18F2680ISPQTP датащи(PDF) 391 Page - Microchip Technology

номер детали PIC18F2680ISPQTP
подробное описание детали  28/40/44-Pin Enhanced Flash Microcontrollers with ECAN??Technology, 10-Bit A/D and nanoWatt Technology
PDF  482 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F2680ISPQTP датащи(HTML) 391 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 389
PIC18F2585/2680/4585/4680
NEGF
Negate f
Syntax:
NEGF
f {,a}
Operands:
0
≤ f ≤ 255
a
∈ [0,1]
Operation:
( f ) + 1
→ f
Status Affected:
N, OV, C, DC, Z
Encoding:
0110
110a
ffff
ffff
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
REG, 1
Before Instruction
REG
=
0011 1010
[3Ah]
After Instruction
REG
=
1100 0110
[C6h]
NOP
No Operation
Syntax:
NOP
Operands:
None
Operation:
No operation
Status Affected:
None
Encoding:
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
Description:
No operation.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
Example:
None.



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