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PSD813F2 датащи(PDF) 101 Page - STMicroelectronics |
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PSD813F2 датащи(HTML) 101 Page - STMicroelectronics |
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101 / 128 page ![]() PSD8XXFX AC/DC parameters Doc ID 7833 Rev 7 101/128 Figure 40. Synchronous clock mode timing – PLD tARPW CPLD register clear or preset pulse width 25 30 35 + 20 ns tARD CPLD array delay Any macrocell 25 29 33 + 4 ns 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. Table 49. CPLD combinatorial timing (3 V devices) (continued) Symbol Parameter Conditions -12 -15 -20 PT Aloc Turbo off Slew rate (1) Unit Min Max Min Max Min Max tCH tCL tCO tH tS CLKIN INPUT REGISTERED OUTPUT AI02860 Table 50. CPLD macrocell Synchronous clock mode timing (5 V devices) Symbol Parameter Conditions -70 -90 -15 Fast PT Aloc Turbo off Slew rate (1) Unit Min Max Min Max Min Max fMAX Maximum frequency External feedback 1/(tS+tCO) 40.0 30.30 25.00 MHz Maximum frequency Internal feedback (fCNT) 1/(tS+tCO–10) 66.6 43.48 31.25 MHz Maximum frequency Pipelined data 1/(tCH+tCL) 83.3 50.00 35.71 MHz tS Input setup time 12 15 20 + 2 + 10 ns tH Input hold time 0 0 0 ns tCH Clock high time Clock input 6 10 15 ns tCL Clock low time Clock input 6 10 15 ns tCO Clock to output delay Clock input 13 18 22 – 2 ns Obsolete Product(s) - Obsolete Product(s) |
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