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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8548ECPXATJB датащи(PDF) 142 Page - Freescale Semiconductor, Inc |
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MPC8548ECPXATJB датащи(HTML) 142 Page - Freescale Semiconductor, Inc |
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142 / 151 page  MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 142 Freescale Semiconductor System Design Information Figure 63. JTAG Interface Connection HRESET From Target Board Sources COP_HRESET 13 COP_SRESET SRESET NC 11 COP_VDD_SENSE2 6 5 15 10 10 k 10 k COP_CHKSTP_IN CKSTP_IN 8 COP_TMS COP_TDO COP_TDI COP_TCK TMS TDO TDI 9 1 3 4 COP_TRST 7 16 2 10 12 (if any) 14 3 Notes: 3. The KEY location (pin 14) is not physically present on the COP header. 10 k TRST1 10 k 10 k 10 k CKSTP_OUT COP_CHKSTP_OUT 3 13 9 5 1 6 10 15 11 7 16 12 8 4 KEY No pin COP Connector Physical Pinout 1 2 NC SRESET 2. Populate this with a 10 resistor for short-circuit/current-limiting protection. NC OVDD 10 k HRESET1 in order to fully control the processor as shown here. 4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for 1. The COP port and target board must be able to independently assert HRESET and TRST to the processor improved signal integrity. TCK 4 5 5. This switch is included as a precaution for BSDL testing. The switch must be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch must be 10 k 6 6. Asserting SRESET causes a machine check interrupt to the e500 core. A B closed to position B. |
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