S12OSCV2D datasheet(105/126 Pages) FREESCALE

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MC9S12DJ64 Device User Guide — V01.17

105

A.5 Reset, Oscillator and PLL

This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and

Phase-Locked-Loop (PLL).

A.5.1 Startup

Table A-14 summarizes several startup characteristics explained in this section. Detailed description of

the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.

Table A-14 Startup Characteristics

A.5.1.1 POR

The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid

if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check

are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self

clock. The fastest startup time possible is given by nuposc.

A.5.1.2 SRAM Data Retention

Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing

code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset

the PORF bit in the CRG Flags Register has not been set.

A.5.1.3 External Reset

When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal

reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an

oscillation before reset.

A.5.1.4 Stop Recovery

Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR

is performed before releasing the clocks to the system.

Conditions are shown in Table A-4 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

T POR release level

VPORR

2.07

T POR assert level

VPORA

0.97

D Reset input pulse width, minimum input time

PWRSTL

tosc

D Startup from Reset

nRST

192

196

nosc

D Interrupt pulse width, IRQ edge-sensitive mode

PWIRQ

D Wait recovery startup time

tWRS

tcyc

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