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OMAP3530ECBC датащи(PDF) 209 Page - Texas Instruments

номер детали OMAP3530ECBC
подробное описание детали  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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OMAP3530ECBC датащи(HTML) 209 Page - Texas Instruments

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mcbspx_clkx
mcbspx_fsx
mcbspx_dx
D7
D6
D5
B8
B5
B6
030-075
6.6.1.2 McBSP in TDM—Multipoint Mode (McBSP3)
OMAP3530/25 Applications Processor
www.ti.com
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
Figure 6-40. McBSP Falling Edge Transmit Timing in Slave Mode
For TDM application in multipoint mode, OMAP3530/25 is considered as a slave. Table 6-69 and
Table 6-70 assume testing over the operating conditions and electrical characteristic conditions described
below.
Table 6-68. McBSP3 Timing Conditions—TDM in Multipoint Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
MIN
MAX
Input Conditions
tR
Input signal rising time
1.0
8.5
ns
tF
Input signal falling time
1.0
8.5
ns
Output Conditions
CLOAD
Output Load Capacitance
40
pF
Table 6-69. McBSP3 Timing Requirements—TDM in Multipoint Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
tW(CLKH)
Cycle Time, mcbsp3_clkx
162.8
162.8
ns
tW(CLKH)
Typical Pulse duration, mcbsp3_clkx high
0.5*P(2)
0.5*P(2)
ns
tW(CLKL)
Typical Pulse duration, mcbsp3_clkx low
0.5*P(2)
0.5*P(2)
ns
tdc(CLK)
Duty cycle error, mcbsp3_clkx
–8.14
8.14
–8.14
8.14
ns
B3(3)
tsu(DRV-CLKAE)
Setup time, mcbsp3_dr valid before
9
9
ns
mcbsp3_clkx active edge
B4(3)
th(CLKAE-DRV)
Hold time, mcbsp3_dr valid after mcbsp3_clkx
2.4
2.4
ns
active edge
B5(3)
tsu(FSV-CLKAE)
Setup time, mcbsp3_fsx valid before
9
9
ns
mcbsp3_clkx active edge
B6(3)
th(CLKAE-FSV)
Hold time, mcbsp3_fsx valid after
2.4
2.4
ns
mcbsp3_clkx active edge
(1)
For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).
(2)
P = mcbsp3_clkx period in ns
(3)
See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures.
Table 6-70. McBSP3 Switching Characteristics—TDM in Multipoint Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B8(2)
td(CLKXAE-DXV)
Delay time, mcbsp3_clkx active edge to
0.6
16.8
0.6
29.6
ns
mcbsp3_dx valid
(1)
For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).
(2)
See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures.
Submit Documentation Feedback
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
209



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