PIC12CE673 datasheet(106/130 Pages) MICROCHIP

106 / 130 page

PIC12C67X

DS30561C-page 106

 1997-2013 Microchip Technology Inc.

FIGURE 12-9: A/D CONVERSION TIMING

TABLE 12-8:

A/D CONVERSION REQUIREMENTS

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

130

TAD

A/D clock period

PIC12C67X

1.6

—

sTOSC based, VREF  3.0V

PIC12LC67X

2.0

—

sTOSC based, VREF full range

PIC12C67X

2.0

4.0

6.0

sA/D RC Mode

PIC12LC67X

3.0

6.0

9.0

sA/D RC Mode

131

TCNV

Conversion time (not including S/H

time) (Note 1)

—

TAD

132

TACQ

Acquisition time

Note 2

—

s

The minimum time is the

amplifier setting time. This

may be used if the "new"

input voltage has not

changed by more than 1 LSb

(i.e., 20.0 mV @ 5.12V) from

the last sampled voltage (as

stated on CHOLD).

134

TGO

Q4 to A/D clock start

—

TOSC/2 §

—

If the A/D clock source is

selected as RC, a time of

TCY is added before the A/D

clock starts. This allows the

SLEEP

instruction to be exe-

cuted.

135

TSWC

Switching from convert

 sample time

1.5 §

—

TAD

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25

C unless otherwise stated. These parameters are for design guidance only and

are not tested.

This specification ensured by design.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 8.1 for min. conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(TOSC/2)(1)

432

Note 1:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

1 TCY

134

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