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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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INTEDG датащи(PDF) 322 Page - Microchip Technology |
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INTEDG датащи(HTML) 322 Page - Microchip Technology |
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322 / 478 page  PIC16(L)F1946/47 DS41414D-page 322 2010-2012 Microchip Technology Inc. FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) CREN bit RXx/DTx Write to bit SREN SREN bit RCxIF bit (Interrupt) Read RCxREG ‘0’ bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ‘0’ Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TXx/CKx pin TXx/CKx pin pin (SCKP = 0) (SCKP = 1) TABLE 25-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 309 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 309 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 93 PIE4 — — RC2IE TX2IE — — BCL2IE SSP2IE 96 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 97 PIR4 — — RC2IF TX2IF — — BCL2IF SSP2IF 100 RC1REG EUSART1 Receive Register 302* RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 308 RC2REG EUSART2 Receive Register 302* RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 308 SP1BRGL EUSART1 Baud Rate Generator, Low Byte 310* SP1BRGH EUSART1 Baud Rate Generator, High Byte 310* SP2BRGL EUSART2 Baud Rate Generator, Low Byte 310* SP2BRGH EUSART2 Baud Rate Generator, High Byte 310* TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 302 TX2STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 307 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception. * Page provides register information. |
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