INTEDG datasheet(244/478 Pages) MICROCHIP

244 / 478 page

PIC16(L)F1946/47

DS41414D-page 244

 2010-2012 Microchip Technology Inc.

The I2C interface supports the following modes and

features:

•Master mode

• Slave mode

• Byte NACKing (Slave mode)

• Limited Multi-master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

• Clock stretching

• Bus collision detection

• General call address matching

•Address masking

• Address Hold and Data Hold modes

• Selectable SDAx hold times

Figure 24-2 is a block diagram of the I2C interface mod-

ule in Master mode. Figure 24-3 is a diagram of the I2C

interface module in Slave mode.

The PIC16F1947 has two MSSP modules, MSSP1 and

MSSP2, each module operating independently from

the other.

FIGURE 24-2:

MSSPX BLOCK DIAGRAM (I2C™ MASTER MODE)

Note 1:

In devices with more than one MSSP

module, it is very important to pay close

attention to SSPxCONx register names.

SSP1CON1 and SSP1CON2 registers

control different operational aspects of

the same module, while SSP1CON1 and

SSP2CON1 control the same features for

two different modules.

Throughout this section, generic refer-

ences to an MSSP module in any of its

operating modes may be interpreted as

being equally applicable to MSSP1 or

MSSP2. Register names, module I/O sig-

nals, and bit names may use the generic

designator ‘x’ to indicate the use of a

numeral to distinguish a particular module

when required.

Read

Write

SSPxSR

Start bit, Stop bit,

Start bit detect,

SSPxBUF

Internal

data bus

Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV

Shift

Clock

MSb

LSb

SDAx

Acknowledge

Generate (SSPxCON2)

Stop bit detect

Write collision detect

Clock arbitration

State counter for

end of XMIT/RCV

SCLx

SCLx in

Bus Collision

SDAx in

[SSPM 3:0]

Baud Rate

Reset SEN, PEN (SSPxCON2)

Generator

(SSPxADD)

Address Match detect

Set SSPxIF, BCLxIF

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