ANSELA datasheet(133/222 Pages) MICROCHIP

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DS22331A-page 133

MCP19111

23.0

TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (independent of Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

Figure 23-1 is a block diagram of the Timer0 module.

FIGURE 23-1:

BLOCK DIAGRAM OF THE TIMER0

23.1

Timer0 Operation

The Timer0 module can be used as either an 8-bit timer

or an 8-bit counter.

23.1.1

8-BIT TIMER MODE

The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-Bit Timer mode is

selected by clearing the T0CS bit of the OPTION_REG

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

23.1.2

8-BIT COUNTER MODE

In 8-Bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin. The

incrementing edge is determined by the T0SE bit of the

OPTION_REG register.

8-Bit Counter mode using the T0CKI pin is selected by

setting the T0CS bit in the OPTION_REG register to ‘1’.

23.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignment is controlled by the PSA bit of the

OPTION_REG register. To assign the prescaler to

Timer0, the PSA bit must be cleared to ‘0’.

There are 8 prescaler options for the Timer0 module

ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION_REG

Timer0 module, the prescaler must be disabled by

setting the PSA bit of the OPTION_REG register.

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing to

the TMR0 register will clear the prescaler.

T0CKI

TMR0SE

TMR0

PS<2:0>

Data Bus

Set Flag bit TMR0IF

on Overflow

TMR0CS

8-bit

Prescaler

FOSC/4

PSA

Sync

2 TCY

Overflow to Timer1

Note:

The value written to the TMR0 register

can be adjusted, in order to account for

the two instruction cycle delay when

TMR0 is written.

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