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WM8321 датащи(PDF) 253 Page - Wolfson Microelectronics plc |
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WM8321 датащи(HTML) 253 Page - Wolfson Microelectronics plc |
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253 / 253 page ![]() Production Data WM8321 w PD, February 2012, Rev 4.0 253 33 REVISION HISTORY DATE REV DESCRIPTION OF CHANGES CHANGED BY October 2010 2.0 SDOUT1 description amended to Open Drain, with external pull-up required. PH December 2010 2.0 Default value of PWRSTATE_DLY corrected. Undervoltage margin specified for all DC-DC converters. Overvoltage margin specified for DC-DC converters 1,2. Chip Temperature (AUX_DATA) equation updated. PH 07/03/11 2.0 Added notes that SLEEP > OFF is not a controlled transition; converters and regulators are disabled immediately. RESET pin description updated to note integrated pull-up. IRQ description updated to note pull-up in Open Drain mode. System Reset and Device Reset descriptions updated, consistent with the Summary Table. Recommended external pull-up resistances added in Pin Description. Internal pull-up / pull-down resistances added in Electrical Characteristics. Noted Active High (non-inverted) polarity for GPIO “Power On/Off request” function is not fully supported in development mode. PH 25/03/11 3.0 Noted maximum limit on Software Resets. Also clarification of the maximum number of Watchdog / Undervoltage Device Resets. Correction to DBVDD test conditions (Section 7.7). RTC_PINT_FREQ definition updated. DC-DC output inductor saturation limit recommendations added. SYSOK_THR register description updated. Quiescent current characteristics updated for DC-DC 1-4. PH 15/09/11 4.0 Backup battery power updated; Charger control registers deleted. LDO11 output amended for LDO11_VSEL_SRC=1 and DC-DC1 disabled. OTP Register Map overview correction (GPn_TRI replaced with GPn_ENA). LDO11 maximum output current increased (only for PVDD ≥ 3.1V). PH 01/02/12 4.0 Electrical Characteristics updated. DC3_STNBY_LIM, DC4_STNBY_LIM descriptions updated. SYSOK_THR description updated. PH 14/02/12 4.0 Product status updated to Production Data JMacD |
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