WM8321 datasheet(110/253 Pages) WOLFSON

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WM8321

Production Data

PD, February 2012, Rev 4.0

110

GPn_FN

GPIO OUTPUT

FUNCTION

DESCRIPTION

External Power

Enable 1

Logic output assigned to one of the timeslots in the ON/OFF

and SLEEP/WAKE sequences. This can be used for sequenced

control of external circuits. See Section 15.3.

External Power

Enable 2

Logic output assigned to one of the timeslots in the ON/OFF

and SLEEP/WAKE sequences. This can be used for sequenced

control of external circuits. See Section 15.3.

System Supply

Good (PVDD

Good)

Logic output from PVDD monitoring circuit. This function

represents the internal SYSOK signal. See Section 24.4.

Converter Power

Good

(PWR_GOOD)

Status output indicating that all selected DC-DC converters and

LDO regulators are operating correctly. Only asserted in ON

and SLEEP modes. See Section 15.13.

External Power

Clock

2MHz clock output suitable for clocking external DC-DC

converters. This clock signal is synchronized with the WM8321

DC Converters clocking signal. See Section 13.

This clock output is only enabled when either of the External

Power Enable signals (EPE1 or EPE2) is asserted. These

signals can be assigned to one of the timeslots in the ON/OFF

and SLEEP/WAKE sequences. See Section 15.3.

Auxiliary Reset

Logic output indicating a Reset condition. This signal is

asserted in the OFF state. The status in SLEEP mode is

configurable. See Section 11.7.

Note that the default polarity for this function (GPn_POL=1) is

“Active High”. Setting GPn_POL=0 will select “Active Low”

function.

Table 53 List of GPIO Output Functions

21.3 CONFIGURING GPIO PINS

The GPIO pins are configured using the Resister fields defined in Table 54.

The function of each GPIO is selected using the GPn_FN register field. The pin direction field

GPn_DIR selects between input functions and output functions. See Section 21.2 for a summary of

the available GPIO functions.

The polarity of each GPIO can be configured using the GPn_POL bits. This inversion is effective both

on GPIO inputs and outputs. When GPn_POL = 1, the non-inverted ‘Active High’ polarity applies. The

opposite logic can be selected by setting GPn_POL = 0.

The voltage power domain of each GPIO is determined by the GPn_PWR_DOM register. Note that

the available options vary between different GPIO pins, as described in Table 56.

A GPIO output may be either CMOS driven or Open Drain. This is selected using the GPn_OD bits.

Internal pull-up or pull-down resistors can be enabled on each pin using the GPn_PULL field. Both

resistors are available for use when the associated GPIO is an input. When the GPIO pin is

configured as an Open Drain output, the internal pull-up resistor may be required if no external pull-up

resistors are present.

A GPIO pin may be tri-stated using the GPn_ENA register field. When GPn_ENA = 0, the respective

pin is tri-stated. A tri-stated pin exhibits high impedance to any external circuit and is disconnected

from the internal GPIO circuits. The pull-up and pull-down resistors are disabled when a GPIO pin is

tri-stated.

GPIO pins can generate an interrupt (see Section 21.4). The GPn_INT_MODE field selects whether

the interrupt occurs on a single active edge only, or else on both rising and falling edges. When single

edge is selected, the active edge is the rising edge (when GPn_POL = 1) or the falling edge (when

GPn_POL = 0).

When GPIO10, GPIO11 or GPIO12 is used as an input to the AUXADC (see Section 18), it is

recommended that the respective GPIO(s) are tri-stated (ie. GPn_ENA = 0). The normal GPIO

functionality cannot be supported on a GPIO pin that is enabled as an input to the AUXADC.

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