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SPEAR1340 датащи(PDF) 135 Page - STMicroelectronics

номер детали SPEAR1340
подробное описание детали  Dual-core Cortex A9 HMI embedded MPU
PDF  200 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR1340 датащи(HTML) 135 Page - STMicroelectronics

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SPEAr1340
Electrical characteristics
Doc ID 023063 Rev 4
135/200
This implies:
Cext = (CL-CS)*2
Example:
For the Aker C2E-24.000-12-3030-X crystal, CL = 12 PF
With CS = 3 PF, we have: Cext = CL1 = CL2 = 18 PF
MCLK generated from an external clock source
Table 43.
MCLK external user clock source characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fMCLK_XI
External clock
source frequency
No limitation
24(1)
33
MHz
VMCLK_XIH
MCLK_XI input
pin high level
voltage
MCLK_AVDD3V3 -
0.3
MCLK_AVDD3V3
V
VMCLK_XIL
MCLK_XI input
pin low level
voltage
MCLK_GNDSUB
0.3
V
DuCy(MCLK_XI) Duty cycle
(2)
40
60
%
tr(MCLK_XI)
tf(MCLK_XI)
MCLK_XI input
rise and fall time
-5% of the clock
period
+5% of the clock
period
%
CIN(MCLK_XI)
MCLK_XI input
capacitance
7pF
IL(MCLK_XI)
MCLK_XI input
leakage current
MCLK_GNDSUB
≤ V
IN
≤ MCLK_AVDD3V3
±1µA
1.
A frequency of 24 MHz is mandatory to obtain the required operating frequency for all clocks generated by the PLL from the
USB PHY.
2.
An initial delay of 1 µs + 2048
fMCLK_XI cycles occurs for duty cycle detection and internal clock availability.



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