STA381BWS datasheet(121/171 Pages) STMICROELECTRONICS

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STA381BWS

Doc ID 018937 Rev 6

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7.6.2

Invalid input detect mute enable

Setting the IDE bit enables this function, which looks at the input I2S data and automatically

mutes if the signals are perceived as invalid.

7.6.3

Binary output mode clock loss detection

This bit detects loss of input MCLK in binary mode and will output 50% duty cycle.

7.6.4

LRCK double trigger protection

This bit actively prevents double triggering of LRCLK.

7.6.5

IC power-down

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

to power down the power stage, then the master clock to all internal hardware except the I2C

block is gated. This places the IC in a very low power consumption state.

7.6.6

External amplifier power-down

Table 126.

Invalid input detect mute enable

Bit

R/W

RST

Name

Description

R/W

IDE

Setting of 1 enables the automatic invalid input detect mute

Table 127.

Binary output mode clock loss detection

Bit

R/W

RST

Name

Description

R/W

BCLE

Binary output mode clock loss detection enable

Table 128.

LRCK double trigger protection

Bit

R/W

RST

Name

Description

R/W

LDTE

LRCLK double trigger protection enable

Table 129.

IC power-down

Bit

R/W

RST

Name

Description

7R/W

PWDN

0: IC power-down low-power condition

1: IC normal operation

Table 130.

External amplifier power-down

Bit

R/W

RST

Name

Description

R/W

EAPD

0: External power stage power-down active

1: Normal operation

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