STA381BWS datasheet(101/171 Pages) STMICROELECTRONICS

101 / 171 page

STA381BWS

Doc ID 018937 Rev 6

101/171

else

{

BC_RES = 1;// Checksum error detected, set the error bit

}

●

Wait until the BCRES bit goes to 0, meaning that the checksum result bit has started to

be updated and everything is ok. Time-out of this operation (e.g. >1 ms) will indicate

checksum failure, and the MCU will handle this event

●

Enable automatic reset of the device in case of checksum error by setting the BCAUTO

bit. The BCRES bit will then be automatically checked by the STA381BWS, on each

audio frame, and a reset event will be triggered in case of checksum mismatch.

●

Periodically check the BC_RES status. A value of 1 indicates a checksum mismatch

has occurred and, therefore, that the device went through a reset cycle.

The previous example is intended for biquad CRC bank calculation, but it can be easily

extended to MDRC/XOver CRC computation.

6.38

MISC4 (address 0x7E)

The STA381BWS allows direct access to the RAM coefficients bypassing the indirect

access mechanism described in Section 6.24: User-defined coefficient control registers

(addr 0x27 - 0x37). Direct access is implemented as follows.

SMAP

reserved

WRA

CH12

Table 99.

Misc register 4

Bit

R/W

RST

Name

Description

7R/W

SMAP

‘1’ = NEW MAP

‘0’ = STMAP

1R/W

WRA

‘0’ = normal operations

‘1’ = enables the write-all procedure when using the

RAM coefficients direct access

0R/W

CH12

‘0’ = normal operations

‘1’ = enables the RAM coefficients direct access

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