MPC5643L datasheet(129/136 Pages) FREESCALE

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Document revision history

MPC5643L Microcontroller Data Sheet, Rev. 8.1

Freescale Semiconductor

129

31 Aug 2010 Editorial changes and improvements.

Revised the Overview section.

Replaced references to PowerPC with references to Power Architecture.

In the feature summary, changed “As much as 128 KB on-chip SRAM” to “128 KB on-chip

SRAM”.

In the “Feature details” section:

• In the “On-chip SRAM with ECC” section, added information about required RAM wait

states.

• In the PIT section, deleted “32-bit counter for real time interrupt, clocked from main

external oscillator” (not supported on this device).

• In the flash-memory section, changed “16 KB Test” to “16 KB test sector”, revised the

wait state information, and deleted the associated Review_Q&A content.

• In the SRAM section, revised the wait state information.

In the 144-pin pinout diagram:

• Renamed pin 58 (was VDD_HV_ADV0_ADV1, is VDD_HV_ADV).

• Renamed pin 59 (was VSS_HV_ADV0_ADV1, is VSS_HV_ADV).

In the “144 LQFP pin function summary” table, for pin 39, changed VSS_LV_COR to

VDD_LV_COR.

In the “Supply pins” table:

• Changed the description for VDD_LV_COR (was “Voltage regulator supply voltage”, is

“Core logic supply”).

• Changed the description for VDD_HV_PMU (was “Core regulator supply”, is “Voltage

regulator supply”).

In the “Pin muxing” table:

• In the “Pad speed” column headings, changed “SRC = 0” to “SRC = 1” and “SRC = 1”

to “SRC = 0”

• For port B[6], changed the pad speed for SRC=0 (was M, is F).

In the “Thermal characteristics” section, added meaningful values to the

thermal-characteristics tables.

Added the “SWG electrical specifications” section.

In the “Voltage regulator electrical characteristics” section, changed the table title (was

“HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD electrical

specifications”, is “Voltage regulator electrical characteristics”) and revised the table.

In the “BCP68 board schematic example” figure, removed the resistor at the base of the

BCP68 transistor.

In the “DC electrical characteristics” table:

• Changed the guarantee parameter for IINJ (was P, is T).

• Added a specification for input leakage current for shared ADC input-only ports.

Revised the “Flash memory module life” table.

In the “FMPLL electrical characteristics” table, revised the footnote defining fSCM and

fVCO.

In the “Main oscillator electrical characteristics” table:

• Changed the max specification for gmXOSCHS (was 11.8 mA/V, is 13.25 mA/V).

• Revised the conditions for TXOSCHSSU.

In the ‘RC oscillator electrical characteristics” table, deleted the specification for



RCMTRIM.

Revised the “ADC conversion characteristics” table.

(cont.)

31 Aug 2010

(cont.)

In the “RESET pin characteristics” section, changed “nRSTIN” to “RESET”.

Added the “Reset sequence” section.

Revised the footnotes in the “Nexus debug port timing” table.

In the “Orderable part number summary” table, added a footnote about frequency

modulation to the “Speed (MHz)” column heading.

Table 41. Revision history (continued)

Revision

Date

Description of changes

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