MPC5634M datasheet(108/132 Pages) FREESCALE

108 / 132 page

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

108

tHI

Data Hold Time for Inputs

D Master (MTFE = 0)

–4

—

–4

—

–4

—

D Slave

7—7—7—

D Master (MTFE = 1,

CPHA = 0)7

—

D Master (MTFE = 1,

CPHA = 1)

–4

—

–4

—

–4

—

tSUO

Data Valid (after SCK edge)

D Master (MTFE = 0)

—6—6—6

D Slave

—25—25

—25

D Master (MTFE = 1,

CPHA=0)

—45—25

—21

Master (MTFE = 1,

CPHA=1)

—6—6—6

tHO

Data Hold Time for Outputs

D Master (MTFE = 0)

–5

—

–5

—

–5

—

D Slave

5.5

—

5.5

—

5.5

—

D Master (MTFE = 1,

CPHA = 0)

8—4—3—

D Master (MTFE = 1,

CPHA = 1)

–5

—

–5

—

–5

—

1 All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad

types of S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0–5.25 V,

TA = TL to TH, and CL = 50 pF with SRC = 0b11.

2 Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency

modulation (FM). 42 MHz parts allow for 40 MHz system clock + 2% FM; 62 MHz parts allow for a 60 MHz system

clock + 2% FM, and 82 MHz parts allow for 80 MHz system clock + 2% FM.

3 The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are

calculated based on two MPC5634M devices communicating over a DSPI link.

4 The actual minimum SCK cycle time is limited by pad performance.

5 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].

6 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

7 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.

Table 37. DSPI timing1,2 (continued)

Symbol

Characteristic

40 MHz

60 MHz

80 MHz

Unit

Min.

Max.

Min.

Max.

Min.

Max.

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