ST10F272Z2T3 datasheet(184/189 Pages) STMICROELECTRONICS

184 / 189 page

Electrical characteristics

ST10F272Z2

184/189

Figure 65.

SSC slave timing

The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock

edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading

clock edge is low-to-high transition (SSCPO = 0b).

The bit timing is repeated for all bits to be transmitted or received.

t317

Read data setup time before latch

edge, phase error detection off

(SSCPEN = 0)

6–

–

t318

Read data hold time after latch

edge, phase error detection off

(SSCPEN = 0)

–

2TCL + 6

–

Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with

48 MHz CPU clock and <SSCBR> set to ‘2h’. When 40 MHz CPU clock is used the maximum baudrate cannot be higher

than 6.6 Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only

with CPU clock lower than 32 MHz (after checking that resulting timings are suitable for the master).

Formula for SSC Clock Cycle time: t310 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.

Minimum limit allowed for t310 is 125 ns (corresponding to 8Mbaud).

Table 84.

SSC slave mode timings (continued)

Symbol

Parameter

Max. Baudrate

6.6 MBd (1))

@fCPU = 40 MHz

(<SSCBR> = 0002h)

Variable Baudrate

(<SSCBR> = 0001h -

FFFFh)

Unit

min.

max.

min.

max.

1st out bit

Last out bit

2nd out bit

2nd in bit

1st in bit

Last in bit

SCLK

MRST

MTSR

t313

t314

t315

t316

t315

t317 t318

t315

t310

t311

t312

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