PIC16F720-ESLASHML datasheet(169/244 Pages) MICROCHIP

169 / 244 page

 2010 Microchip Technology Inc.

DS41430A-page 169

PIC16F/LF720/721

19.0

POWER-DOWN MODE (SLEEP)

The Power-down mode is entered by executing a

SLEEP

instruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running.

•PD bit of the STATUS register is cleared.

•TO bit of the STATUS register is set.

• Oscillator driver is turned off.

• I/O ports maintain the status they had before

SLEEP

was executed (driving high, low or high-

impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD or VSS, with no external

circuitry drawing current from the I/O pin. I/O pins that

are high-impedance inputs should be pulled high or low

externally to avoid switching currents caused by float-

ing inputs. The T0CKI input should also be at VDD or

VSS for lowest current consumption. The contribution

from on-chip pull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level when

external MCLR is enabled.

19.1

Wake-up from Sleep

The device can wake-up from Sleep through one of the

following events:

External Reset input on MCLR pin.

Watchdog

Timer

wake-up

(if

WDT

was

enabled).

Interrupt from RA2/INT pin, PORTB change or a

peripheral interrupt.

The first event will cause a device Reset. The two latter

events are considered a continuation of program

execution. The TO and PD bits in the STATUS register

can be used to determine the cause of a device Reset.

The PD bit, which is set on power-up, is cleared when

Sleep is invoked. TO bit is cleared if WDT wake-up

occurred.

The following peripheral interrupts can wake the device

from Sleep:

TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.

USART Receive Interrupt (Synchronous Slave

mode only)

A/D conversion (when A/D clock source is RC)

Interrupt-on-change

External interrupt from INT pin

Capture event on CCP1

SSP interrupt in SPI or I2C Slave mode

Other peripherals cannot generate interrupts since

during Sleep, no on-chip clocks are present.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction, then branches to the interrupt

address (0004h). In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

Note:

A Reset generated by a WDT time-out

does not drive MCLR pin low.

Note:

If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the correspond-

ing interrupt flag bits set, the device will

immediately wake-up from Sleep. The

SLEEP

instruction is completely executed.

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