PIC16F720-ESLASHML datasheet(136/244 Pages) MICROCHIP

136 / 244 page

PIC16F/LF720/721

DS41430A-page 136

 2010 Microchip Technology Inc.

16.3.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the AUSART

for synchronous slave operation:

• SYNC = 1

• CSRC = 0

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TXSTA register configures the device as a slave.

Clearing the SREN and CREN bits of the RCSTA register

ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

AUSART.

16.3.2.1

AUSART Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave

modes

are

identical

(refer

Section 16.3.1.2

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

If two words are written to the TXREG and then the

SLEEP

instruction is executed, the following will occur:

The first character will immediately transfer to

the TSR register and transmit.

The second word will remain in TXREG register.

The TXIF bit will not be set.

After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

16.3.2.2

Synchronous Slave Transmission

Setup

Set the SYNC and SPEN bits and clear the

CSRC bit.

Clear the CREN and SREN bits.

If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

TXIE bit.

If 9-bit transmission is desired, set the TX9 bit.

Enable transmission by setting the TXEN bit.

Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

Start

transmission

writing

the

Least

Significant 8 bits to the TXREG register.

TABLE 16-8:

REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE

PEIE

TMR0IE

INTE

RABIE

TMR0IF

INTF

RABIF

0000 000x

PIE1

TMR1GIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

TRISC

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

1111 1111

TXREG

AUSART Transmit Data Register

0000 0000

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

Legend:

= unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave transmission.

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