HCS12 datasheet(295/452 Pages) FREESCALE

295 / 452 page

Glossary

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

295

Operation:

If (Counter)

≠ 0, then (PC) + $0003 + Rel ⇒ PC

Description:

Tests the specified counter register A, B, D, X, Y, or SP. If the counter

encoded into three bytes of machine code including a 9-bit relative offset

(–256 to +255 locations from the start of the next instruction).

DBNE and IBNE instructions are similar to TBNE, except that the counter is

decremented or incremented rather than simply being tested. Bits 7 and 6

of the instruction postbyte are used to determine which operation is to be

performed.

TBNE

Test and Branch if Not Equal to Zero

TBNE

CCR Details:

HIN

––––––––

Source Form

Address

Mode

Object Code(1)

1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (TBEQ –

0) or not zero (TBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should be 0:1 for TBNE.

Access Detail

HCS12

M68HC12

TBNE abdxys,rel9

REL

04 lb rr

PPP/PPO

PPP

Count

Bits 2:0

Source Form

Object Code

(If Offset is Positive)

Object Code

(If Offset is Negative)

000

001

TBNE A, rel9

TBNE B, rel9

04 60 rr

04 61 rr

04 70 rr

04 71 rr

100

101

110

111

TBNE D, rel9

TBNE X, rel9

TBNE Y, rel9

TBNE SP, rel9

04 64 rr

04 65 rr

04 66 rr

04 67 rr

04 74 rr

04 75 rr

04 76 rr

04 77 rr

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