PIC12F1822-ISLASHMF datasheet(353/398 Pages) MICROCHIP

353 / 398 page

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 353

PIC12F/LF1822/16F/LF1823

TABLE 29-5:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

FIGURE 29-10:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C

TA +125°C

Param

No.

Sym.

Characteristic

Min.

Typ† Max. Units

Conditions

TMCLMCLR Pulse Width (low)

—

s

VDD = 3.3-5V, -40°C to +85°C

VDD = 3.3-5V

TWDTLP Low-Power Watchdog Timer

Time-out Period (No Prescaler)

VDD = 3.3V-5V

TOST

Oscillator Start-up Timer Period(1), (2)

—

1024

—

Tosc (Note 3)

33*

TPWRT

Power-up Timer Period, PWRTE = 0

140

34*

TIOZ

I/O high-impedance from MCLR Low

or Watchdog Timer Reset

——

2.0

s

VBOR

Brown-out Reset Voltage

2.38

1.80

2.5

1.9

2.65

2.05

VBORV=2.5V

BORV=1.9V

36*

VHYST

Brown-out Reset Hysteresis

-40°C to +85°C

37*

TBORDC Brown-out Reset DC Response

Time

135

sVDD  VBOR

These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at “min” values with an external

clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no

clock) for all devices.

2: By design.

3: Period of the slower clock.

4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1

F and 0.01 F values in parallel are recommended.

T0CKI

T1CKI

TMR0 or

TMR1

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