PIC12F1822-ISLASHMF datasheet(305/398 Pages) MICROCHIP

305 / 398 page

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 305

PIC12F/LF1822/16F/LF1823

25.4.2.3

EUSART Synchronous Slave

Reception

The operation of the Synchronous Master and Slave

modes is identical (Section 25.4.1.5 “Synchronous

Master Reception”), with the following exceptions:

• Sleep

• CREN bit is always set, therefore the receiver is

never Idle

• SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE enable bit is set, the

interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

25.4.2.4

Synchronous Slave Reception

Set-up:

Set the SYNC and SPEN bits and clear the

CSRC bit.

Clear the ANSEL bit for both the CK and DT pins

(if applicable).

If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

If 9-bit reception is desired, set the RX9 bit.

Set the CREN bit to enable reception.

The RCIF bit will be set when reception is

complete. An interrupt will be generated if the

RCIE bit was set.

If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

Retrieve the 8 Least Significant bits from the

receive FIFO by reading the RCREG register.

If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

the EUSART.

TABLE 25-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

BAUDCON

ABDOVF

RCIDL

—SCKP

BRG16

—

WUE

ABDEN

290

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

PIE1

TMR1GIE

ADIE

RCIE

TXIE

SSP1IE

CCP1IE

TMR2IE

TMR1IE

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSP1IF

CCP1IF

TMR2IF

TMR1IF

RCREG

EUSART Receive Data Register

284*

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

289

TRISC(1)

—

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

125

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

288

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.

* Page provides register information.

Note 1:

PIC16F/LF1823 only.

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