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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM647 датащи(PDF) 156 Page - Texas Instruments |
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TMS320DM647 датащи(HTML) 156 Page - Texas Instruments |
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156 / 181 page  SGMII 0 GMIIport0 Gigabit MAC 0 SGMII1 (A) GMIIport1 2 2 2 AddrLookup Engine SGMII Port0 HostDMA Controller 3 -port Gigabit Switch Gigabit MAC 1 Buffer Descriptor Memory Configuration Registers REFCLK 2 2 SGMII Port1 MII Serial Mgmt Peripheral Bus MDIO Configuration Bus Configuration Bus DSP Interrupt Controller TMS320DM647 TMS320DM648 SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009 www.ti.com • EtherStats and 802.3 Stats RMON statistics gathering (shared) • Programmable statistics interrupt mask when a statistic is above one half its 32-bit value – MDIO module for PHY management – SGMII gigabit current mode logic (CML) differential SERializer/DESerializer (SerDes) I/O receiver/transmitters • Adaptive active equalization for superior data dependent jitter tolerance in the presence of a lossy channel • Loss of signal detector with programmable threshold levels in receive channels • Integrated receiver and transmitter termination • IEEE 802.3 gigabit Ethernet conformant 6.19.1 Ethernet Subsystem Functions A. SGMII port 1 is not available on DM647. Figure 6-51. Ethernet Subsystem Block Diagram The Ethernet Subsystem conforms to the IEEE 802.3-2002 standard. Deviating from this standard, the GMAC module does not use the transmit coding error signal MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the GMAC generates an incorrect checksum by inverting the frame CRC, so that the transmitted frame will be detected as an error by the network. In networking systems, packet transmission and reception are critical tasks. The communications port programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software and communications modules. The CPPI block contains 2048 words of 32-bit buffer descriptor memory that holds up to 512 buffer descriptors. After reset, initialization, configuration, and auto-negotiation, the host C64x+ DSP may initiate Ethernet transmit and receive operations. 156 Peripheral Information and Electrical Specifications Copyright © 2010–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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