ATtiny45 datasheet(117/196 Pages) ATMEL

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117

7598H–AVR–07/09

ATtiny25/45/85

18.5

Changing Channel or Reference Selection

The MUX3..0 and REFS2..0 bits in the ADMUX Register are single buffered through a tempo-

rary register to which the CPU has random access. This ensures that the channels and voltage

reference selection only takes place at a safe point during the conversion. The channel and volt-

age reference selection is continuously updated until a conversion is started. Once the

conversion starts, the channel and voltage reference selection is locked to ensure a sufficient

sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the

conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following

rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel

or voltage reference selection values to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX Register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

When ADATE or ADEN is cleared.

During conversion, minimum one ADC clock cycle after the trigger event.

After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

18.5.1

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

In Single Conversion mode, always select the channel before starting the conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the conversion to complete before changing the channel selection.

In Free Running mode, always select the channel before starting the first conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the first conversion to complete, and then change the channel

selection. Since the next conversion has already started automatically, the next result will reflect

the previous channel selection. Subsequent conversions will reflect the new channel selection.

Table 18-1.

ADC Conversion Time

Condition

Sample & Hold (Cycles from

Start of Conversion)

Total Conversion Time

(Cycles)

First conversion

13.5

Normal conversions

1.5

Auto Triggered conversions

13.5

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