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ICS1893 датащи(PDF) 144 Page - Integrated Circuit Systems |
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ICS1893 датащи(HTML) 144 Page - Integrated Circuit Systems |
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144 / 152 page ![]() ICS1893 Rev C 6/6/00 June, 2000 144 Chapter 10 DC and AC Operating Conditions ICS1893 Data Sheet - Release Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 10.5.18 Reset: Hardware Reset and Power-Down Table 10-25 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • REF_IN • RESETn • TXCLK Figure 10-19 shows the timing diagram for the time periods. Figure 10-19. Hardware Reset and Power-Down Timing Diagram Table 10-25. Hardware Reset and Power-Down Timing Time Period Parameter Condi- tions Min. Typ. Max. Units t1 RESETn Active to Device Isolation and Initialization – – 60 – ns t2 Minimum RESETn Pulse Width – 500 40 – ns t3 RESETn Released to TXCLK Valid – – 35 500 ms REF_IN RESETn t1 t2 t3 TXCLK Valid Power Consumption (AC only) |
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