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ICS1893 датащи(PDF) 135 Page - Integrated Circuit Systems |
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ICS1893 датащи(HTML) 135 Page - Integrated Circuit Systems |
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135 / 152 page ![]() Chapter 10 DC and AC Operating Conditions ICS1893 Rev C 6/6/00 June, 2000 135 ICS1893 - Release Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 10.5.9 10M Media Independent Interface: Receive Latency Table 10-16 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX (that is, the MII TP_RXP and TP_RXN pins) • RXCLK • RXD Figure 10-10 shows the timing diagram for the time periods. Figure 10-10. 10M MII Receive Latency Timing Diagram Table 10-16. 10M MII Receive Latency Time Period Parameter Conditions Min. Typ. Max. Units t1 First Bit of /5/ on TP_RX to /5/D/ on RXD 10M MII – 6.5 7 Bit times † Manchester encoding is not shown. 5 5 D 5 t1 TP_RX† RXCLK RXD |
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