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ATmega128 датащи(PDF) 300 Page - ATMEL Corporation

номер детали ATmega128
подробное описание детали  8-bit Microcontroller with 128K Bytes In-System Programmable Flash
PDF  386 Pages
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производитель  ATMEL [ATMEL Corporation]
домашняя страница  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATmega128 датащи(HTML) 300 Page - ATMEL Corporation

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300
2467S–AVR–07/09
ATmega128
Notes:
1.
tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2.
tWLRH_CE is valid for the Chip Erase command.
Serial
Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in Table 127 on page 300, the pin
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface. Note that throughout the description about Serial downloading, MOSI and MISO
are used to describe the serial data in and serial data out respectively. For ATmega128 these
pins are mapped to PDI and PDO.
SPI Serial
Programming Pin
Mapping
Even though the SPI Programming interface re-uses the SPI I/O module, there is one important
difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPI I/O module are not
used in the Programming interface. Instead, PE0 and PE1 are used for data in SPI Program-
ming mode as shown in Table 127.
tXLPH
XTAL1 Low to PAGEL high
0
ns
tPLXH
PAGEL low to XTAL1 high
150
ns
tBVPH
BS1 Valid before PAGEL High
67
ns
tPHPL
PAGEL Pulse Width High
150
ns
tPLBX
BS1 Hold after PAGEL Low
67
ns
tWLBX
BS2/1 Hold after WR Low
67
ns
tPLWL
PAGEL Low to WR Low
67
ns
tBVWL
BS1 Valid to WR Low
67
ns
tWLWH
WR Pulse Width Low
150
ns
tWLRL
WR Low to RDY/BSY Low
0
1
μs
tWLRH
WR Low to RDY/BSY High
(1)
3.7
5
ms
tWLRH_CE
WR Low to RDY/BSY High for Chip Erase
(2)
7.5
10
ms
tXLOL
XTAL1 Low to OE Low
0
ns
tBVDV
BS1 Valid to DATA valid
0
250
ns
tOLDV
OE Low to DATA Valid
250
ns
tOHDZ
OE High to DATA Tri-stated
250
ns
Table 126. Parallel Programming Characteristics, V
CC = 5 V ± 10% (Continued)
Symbol
Parameter
Min
Typ
Max
Units
Table 127. Pin Mapping SPI Serial Programming
Symbol
Pins
I/O
Description
MOSI (PDI)
PE0
I
Serial data in
MISO (PDO)
PE1
O
Serial data out
SCK
PB1
I
Serial clock



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