ATmega128 datasheet(281/386 Pages) ATMEL

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281

2467S–AVR–07/09

ATmega128

Setting the Boot

Loader Lock Bits by

SPM

To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR

and execute SPM within four clock cycles after writing SPMCSR. The only accessible lock bits

are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft-

ware update by the MCU.

See Table 108 and Table 109 for how the different settings of the Boot Loader Bits affect the

Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an

SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR.

The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to

load the Z-pointer with $0001 (same as used for reading the Lock bits). For future compatibility It

is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the lock-bits. When pro-

gramming the Lock Bits the entire Flash can be read during the operation.

EEPROM Write

Prevents Writing to

SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

Reading the Fuse and

Lock Bits from

Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruc-

tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR,

the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN

bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed

within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-

SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.

The algorithm for reading the Fuse Low bits is similar to the one described above for reading the

Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and

SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the

BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low bits (FLB) will be

loaded in the destination register as shown below. Refer to Table 119 on page 288 for a detailed

description and mapping of the Fuse Low bits.

Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM instruc-

tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,

the value of the Fuse High bits (FHB) will be loaded in the destination register as shown below.

Refer to Table 118 on page 288 for detailed description and mapping of the Fuse High bits.

When reading the Extended Fuse bits, load $0002 in the Z-pointer. When an LPM instruction is

executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the

value of the Extended Fuse bits (EFB) will be loaded in the destination register as shown below.

Refer to Table 117 on page 287 for detailed description and mapping of the Fuse High bits.

Bit

765

432

BLB12

BLB11

BLB02

BLB01

Bit

765

432

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

Bit

210

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Bit

210

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Bit

210

––

–

––

EFB1

EFB0

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