ATmega128 datasheet(204/386 Pages) ATMEL

204 / 386 page

204

2467S–AVR–07/09

ATmega128

Overview of the

TWI Module

The TWI module is comprised of several submodules, as shown in Figure 94. All registers drawn

in a thick line are accessible through the AVR data bus.

Figure 94. Overview of the TWI Module

Scl and SDA Pins

These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a

slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike

suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR

pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as

explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need

for external ones.

Bit Rate Generator

Unit

This unit controls the period of SCL when operating in a Master mode. The SCL period is con-

trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status

CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note

that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock

period. The SCL frequency is generated according to the following equation:

•

TWBR = Value of the TWI Bit Rate Register

•

TWPS = Value of the prescaler bits in the TWI Status Register

Note:

Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus

line load. See Table 133 on page 322 for value of pull-up resistor.

Bus Interface Unit

This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and

Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,

or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also

contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-

ter is not directly accessible by the application software. However, when receiving, it can be set

Address Register

(TWAR)

Address Match Unit

Address Comparator

Control Unit

Control Register

(TWCR)

Status Register

(TWSR)

State Machine and

Status control

SCL

Slew-rate

Control

Spike

Filter

SDA

Slew-rate

Control

Spike

Filter

Bit Rate Generator

Bit Rate Register

(TWBR)

Prescaler

Bus Interface Unit

START / STOP

Control

Arbitration detection

Ack

Spike Suppression

Address/Data Shift

SCL frequency

CPU Clock frequency

2(TWBR) 4

TWPS

⋅

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