ATmega128 datasheet(189/386 Pages) ATMEL

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189

2467S–AVR–07/09

ATmega128

USART Register

Description

USARTn I/O Data

The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share

the same I/O address referred to as USARTn Data Register or UDRn. The Transmit Data Buffer

the UDRn Register location will return the contents of the receive data buffer register (RXBn).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to

zero by the Receiver.

The transmit buffer can only be written when the UDREn flag in the UCSRAn Register is set.

Data written to UDRn when the UDREn flag is not set, will be ignored by the USARTn Transmit-

ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter

will load the data into the Transmit Shift Register when the Shift Register is empty. Then the

data will be serially transmitted on the TxDn pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the

receive buffer is accessed. Due to this behavior of the receive buffer, do not use read modify

write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC

and SBIS), since these also will change the state of the FIFO.

USART Control and

Status Register A –

UCSRnA

• Bit 7 – RXCn: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive

buffer is empty (i.e., does not contain any unread data). If the receiver is disabled, the receive

buffer will be flushed and consequently the RXCn bit will become zero. The RXCn flag can be

used to generate a Receive Complete interrupt (see description of the RXCIEn bit).

• Bit 6 – TXCn: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buffer (UDRn). The TXCn flag bit is auto-

matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing

a one to its bit location. The TXCn flag can generate a Transmit Complete interrupt (see descrip-

tion of the TXCIEn bit).

• Bit 5 – UDREn: USART Data Register Empty

The UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is

one, the buffer is empty, and therefore ready to be written. The UDREn flag can generate a Data

UDREn is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FEn: Frame Error

Bit

543

210

RXBn[7:0]

UDRn (Read)

TXBn[7:0]

UDRn (Write)

Read/Write

R/W

Initial Value

Bit

765

4321

RXCn

TXCn

UDREn

FEn

DORn

UPEn

U2Xn

MPCMn

UCSRnA

Read/Write

R/W

Initial Value

001

0000

ATmega128 датащи(PDF) 189 Page - ATMEL Corporation

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