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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega162 датащи(PDF) 268 Page - ATMEL Corporation |
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ATmega162 датащи(HTML) 268 Page - ATMEL Corporation |
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268 / 324 page  268 2513K–AVR–07/09 ATmega162/V SPI Timing Characteristics See Figure 116 and Figure 117 for details. Note: 1. In SPI Programming mode, the minimum SCK high/low period is: – 2 tCLCL for fCK < 12 MHz – 3 t CLCL for fCK > 12 MHz. Figure 116. SPI Interface Timing Requirements (Master Mode) Table 113. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 68 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 • tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 • tck 11 SCK high/low(1) Slave 2 • tck 12 Rise/Fall time Slave 1.6 µs 13 Setup Slave 10 ns 14 Hold Slave tck 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 2 • tck MOSI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB LSB MSB ... ... 61 22 3 45 8 7 |
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