ATmega162 datasheet(225/324 Pages) ATMEL

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225

2513K–AVR–07/09

ATmega162/V

Using the SPM

Interrupt

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the

SPMEN bit in SPMCR is cleared. This means that the interrupt can be used instead of polling

the SPMCR Register in software. When using the SPM interrupt, the Interrupt Vectors should be

moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is

blocked for reading. How to move the interrupts is described in “Interrupts” on page 57.

Consideration while

Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated by leaving

Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the

entire Boot Loader, and further software updates might be impossible. If it is not necessary to

change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to

protect the Boot Loader software from any internal software changes.

Prevent Reading the

RWW Section During

Self-programming

During Self-programming (either Page Erase or Page Write), the RWW section is always

blocked for reading. The user software itself must prevent that this section is addressed during

the self programming operation. The RWWSB in the SPMCR will be set as long as the RWW

section is busy. During Self-programming the Interrupt Vector table should be moved to the BLS

as described in “Interrupts” on page 57, or the interrupts must be disabled. Before addressing

the RWW section after the programming is completed, the user software must clear the

RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on

page 227 for an example.

Setting the Boot

Loader Lock Bits by

SPM

To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCR and

execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the

Boot Lock bits that may prevent the Application and Boot Loader section from any software

update by the MCU.

See Table 89 and Table 90 for how the different settings of the Boot Loader bits affect the Flash

access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an

SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR.

The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to

load the Z-pointer with 0x0001 (same as used for reading the Lock bits). For future compatibility

it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When

programming the Lock bits the entire Flash can be read during the operation.

EEPROM Write

Prevents Writing to

SPMCR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCR Register.

Reading the Fuse and

Lock Bits from

Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruc-

tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR,

the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN

bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed

within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-

SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.

Bit

765

432

BLB12

BLB11

BLB02

BLB01

Bit

765

432

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

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