ATmega162 datasheet(207/324 Pages) ATMEL

207 / 324 page

207

2513K–AVR–07/09

ATmega162/V

IDCODE; 0x1

Optional JTAG instruction selecting the 32-bit ID-register as data register. The ID-Register con-

sists of a version number, a device number and the manufacturer code chosen by JEDEC. This

is the default instruction after Power-up.

The active states are:

•

Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.

•

Shift-DR: The IDCODE scan chain is shifted by the TCK input.

SAMPLE_PRELOAD;

0x2

Mandatory JTAG instruction for preloading the output latches and taking a snapshot of the

input/output pins without affecting the system operation. However, the output latches are not

connected to the pins. The Boundary-scan Chain is selected as Data Register.

The active states are:

•

Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

•

Shift-DR: The Boundary-scan Chain is shifted by the TCK input.

•

Update-DR: Data from the Boundary-scan chain is applied to the output latches. However,

the output latches are not connected to the pins.

AVR_RESET; 0xC

The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or

releasing the JTAG Reset source. The TAP controller is not reset by this instruction. The one bit

Reset Register is selected as data register. Note that the reset will be active as long as there is

a logic 'one' in the Reset Chain. The output from this chain is not latched.

The active states are:

•

Shift-DR: The Reset Register is shifted by the TCK input.

BYPASS; 0xF

Mandatory JTAG instruction selecting the Bypass Register for data register.

The active states are:

•

Capture-DR: Loads a logic “0” into the Bypass Register.

•

Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

Boundary-scan

Related Register in I/O

Memory

MCU Control and

Status Register –

MCUCSR

The MCU Control and Status Register contains control bits for general MCU functions, and pro-

vides information on which reset source caused an MCU Reset.

• Bit 7 – JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this

bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of

the JTAG interface, a timed sequence must be followed when changing this bit: The application

software must write this bit to the desired value twice within four cycles to change its value.

If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to

one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.

Bit

765

432

JTD

–

SM2

JTRF

WDRF

BORF

EXTRF

PORF

MCUCSR

Read/Write

R/W

Initial Value

See Bit Description

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