ATmega162 datasheet(163/324 Pages) ATMEL

163 / 324 page

163

2513K–AVR–07/09

ATmega162/V

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic

zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,

and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-

ter mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 73 and Figure 74 for an example. The CPOL functionality is summa-

rized below:

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of SCK. Refer to Figure 73 and Figure 74 for an example. The CPHA func-

tionality is summarized below:

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have

no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f

osc is

shown in the following table:

Table 66. CPOL Functionality

CPOL

Leading Edge

Trailing Edge

Rising

Falling

Rising

Table 67. CPHA Functionality

CPHA

Leading Edge

Trailing Edge

Sample

Setup

Sample

Table 68. Relationship Between SCK and the Oscillator Frequency

SPI2X

SPR1

SPR0

SCK Frequency

osc/4

osc/16

osc/64

osc/128

osc/2

osc/8

osc/32

osc/64

ATmega162 датащи(PDF) 163 Page - ATMEL Corporation

ATmega162 датащи(HTML) 163 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL