ATmega16 datasheet(239/357 Pages) ATMEL

239 / 357 page

239

2466S–AVR–05/09

ATmega16(L)

Note:

Incorrect setting of the switches in Figure 123 will make signal contention and may damage the part. There are several input

choices to the S&H circuitry on the negative input of the output comparator in Figure 123. Make sure only one path is selected

from either one ADC pin, Bandgap reference source, or Ground.

If the ADC is not to be used during scan, the recommended input values from Table 92 should

be used. The user is recommended not to use the Differential Gain stages during scan. Switch-

cap based gain stages require fast operation and accurate timing which is difficult to obtain

when used in a scan chain. Details concerning operations of the differential gain stage is there-

fore not provided.

The AVR ADC is based on the analog circuitry shown in Figure 123 with a successive approxi-

mation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is

usually to ensure that an applied analog voltage is measured within some limits. This can easily

be done without running a successive approximation algorithm: apply the lower limit on the digi-

tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit

on the digital DAC[9:0] lines, and verify the output from the comparator to be high.

The ADC need not be used for pure connectivity testing, since all analog inputs are shared with

a digital port pin as well.

When using the ADC, remember the following:

•

The Port Pin for the ADC channel in use must be configured to be an input with pull-up

disabled to avoid signal contention.

•

In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when

enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before

MUXEN_2

Input

Input Mux bit 2

MUXEN_1

Input

Input Mux bit 1

MUXEN_0

Input

Input Mux bit 0

NEGSEL_2

Input

Input Mux for negative input for

differential signal, bit 2

NEGSEL_1

Input

Input Mux for negative input for

differential signal, bit 1

NEGSEL_0

Input

Input Mux for negative input for

differential signal, bit 0

PASSEN

Input

Enable pass-gate of gain stages.

PRECH

Input

Precharge output latch of

comparator. (Active low)

SCTEST

Input

Switch-cap TEST enable. Output

from x10 gain stage send out to

Port Pin having ADC_4

Input

Output of gain stages will settle

faster if this signal is high first two

ACLK periods after AMPEN goes

high.

VCCREN

Input

Selects Vcc as the ACC reference

voltage.

Table 92. Boundary-scan Signals for the ADC (Continued)

Signal

Name

Direction as Seen

from the ADC

Description

Recommended

Input when Not

in Use

Output Values when Recommended

Inputs are used, and CPU is not

Using the ADC

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