ATmega16 datasheet(192/357 Pages) ATMEL

192 / 357 page

192

2466S–AVR–05/09

ATmega16(L)

Slave Receiver Mode

In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter

(see Figure 90). All the status codes mentioned in this section assume that the prescaler bits are

zero or are masked to zero.

Figure 90. Data Transfer in Slave Receiver Mode

To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:

The upper seven bits are the address to which the Two-wire Serial Interface will respond when

addressed by a Master. If the LSB is set, the TWI will respond to the general call address ($00),

otherwise it will ignore the general call address.

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable

the acknowledgement of the device’s own Slave address or the general call address. TWSTA

and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own

Slave address (or the general call address if enabled) followed by the data direction bit. If the

direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After

its own Slave address and the write bit have been received, the TWINT Flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 76. The

Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master

mode (see states $68 and $78).

If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA

after the next received data byte. This can be used to indicate that the Slave is not able to

receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own Slave

address. However, the Two-wire Serial Bus is still monitored and address recognition may

resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily

isolate the TWI from the Two-wire Serial Bus.

In all sleep modes other than Idle Mode, the clock system to the TWI is turned off. If the TWEA

bit is set, the interface can still acknowledge its own Slave address or the general call address

by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep

and the TWI will hold the SCL clock low during the wake up and until the TWINT Flag is cleared

(by writing it to one). Further data reception will be carried out as normal, with the AVR clocks

running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may

be held low for a long time, blocking other data transmissions.

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

Value

Device’s Own Slave Address

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

Value

100

Device 3

Device n

SDA

SCL

........

Device 2

MASTER

TRANSMITTER

Device 1

SLAVE

RECEIVER

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