ATmega16 datasheet(167/357 Pages) ATMEL

167 / 357 page

167

2466S–AVR–05/09

ATmega16(L)

• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Char-

acter Size) in a frame the Receiver and Transmitter use.

• Bit 0 – UCPOL: Clock Polarity

This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is

used. The UCPOL bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCK).

USART Baud Rate

Registers – UBRRL

and UBRRH

The UBRRH Register shares the same I/O location as the UCSRC Register. See the “Accessing

UBRRH/ UCSRC Registers” on page 162 section which describes how to access this register.

• Bit 15 – URSEL: Register Select

This bit selects between accessing the UBRRH or the UCSRC Register. It is read as zero when

reading UBRRH. The URSEL must be zero when writing the UBRRH.

• Bit 14:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRH is written.

Table 66. UCSZ Bits Settings

UCSZ2

UCSZ1

UCSZ0

Character Size

000

5-bit

001

6-bit

010

7-bit

011

8-bit

100

Reserved

101

Reserved

110

Reserved

111

9-bit

Table 67. UCPOL Bit Settings

UCPOL

Transmitted Data Changed (Output of

TxD Pin)

Received Data Sampled (Input on

RxD Pin)

Rising XCK Edge

Falling XCK Edge

Rising XCK Edge

Bit

151413121110

URSEL

–

UBRR[11:8]

UBRRH

UBRR[7:0]

UBRRL

765

4321

Read/Write

R/W

Initial Value

000

0000

000

0000

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