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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TPS658620ZQZT датащи(PDF) 84 Page - Texas Instruments |
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TPS658620ZQZT датащи(HTML) 84 Page - Texas Instruments |
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84 / 104 page  3.62.7 LIMIT CHECK SETUP TPS658620 Advanced Power Management Unit SLVS993 – OCTOBER 2009 www.ti.com Table 3-67. ADC0 Output Data ADC0_SUM2(1) [Addr 0x94] Bit Number B7 B6 B5 B4 B3 B2 B1 B0 Bit Name AVG[15] AVG[14] AVG[13] AVG[12] AVG[11] AVG[10] AVG[9] AVG[8] ADC0_SUM1 [Addr 0x95] Bit Name AVG[7] AVG[6] AVG[5] AVG[4] AVG[3] AVG[2] AVG[1] AVG[0] ADC0_MAX2 [Addr 0x96] Bit Name RSVD967 RSVD966 RSVD965 RSVD964 RSVD963 RSVD962 MAX[9] MAX[8] ADC0_MAX1 [Addr 0x97] Bit Name MAX[7] MAX[6] MAX[5] MAX[4] MAX[3] MAX[2] MAX[1] MAX[0] ADC0_MIN2 [Addr 0x98] Bit Name RSVD987 RSVD986 RSVD985 RSVD984 RSVD983 RSVD982 MIN[9] MIN[8] ADC0_MIN1 [Addr 0x99] Bit Name MIN[7] MIN[6] MIN[5] MIN[4] MIN[3] MIN[2] MIN[1] MIN[0] (1) All bits in ADC0_SUM2 are read only. The ADC0 timing engine has configurable low and high thresholds to interrupt the host when conversion values, stored in registers ADC0_MAX and ADC0_MIN exceed a pre-selected range . A limit violation will be detected and an interrupt sent to the host when the sampled value stored in registers ADC0_MAX2, ADC0_MAX1 exceeds the maximum value set in registers ADC0_HILIM2, ADC0_HILIM1 or when the minimum sampled value stored in registers ADC0_MIN2, ADC0_MIN1 is lower than the minimum value programmed in registers and ADC0_HILIM2, ADC0_HILIM1. Limit violations can not occur if Low Limit = 0x000 and High Limit = 0xFFF. Table 3-68. ADC0 Limit Selection ADC0_HILIM2 [Addr 0x63] Bit Number B7 B6 B5 B4 B3 B2 B1 B0 Bit Name RSVD637 RSVD636 RSVD635 RSVD634 HILIMA[11] HILIMA[10] HILIMA[9] HILIMA[8] ADC0_HILIM1 [Addr 0x64] Bit Name HILIMA[7] HILIMA[6] HILIMA[5] HILIMA[4] HILIMA[3] HILIMA[2] HILIMA[1] HILIMA[0] ADC0_LOLIM2 [Addr 0x65] Bit Name RSVD657 RSVD656 RSVD655 RSVD654 LOLIMA[11] LOLIMA[10] LOLIMA[9] LOLIMA[8] ADC0_LOLIM1 [Addr 0x66] Bit Name LOLIMA[7] LOLIMA[6] LOLIMA[5] LOLIMA[4] LOLIMA[3] LOLIMA[2] LOLIMA[1] LOLIMA[0] The limit detection ADC conversion cycle should be configured with internal trigger and sampling sequences as follows: 1. To detect when an individual sample violates the max/min limits: Set RD_MODE[1:0] to 00 and REPEAT to 1. With these settings the ALU will compare the 10-bit ADC data retuned from the SAR engine to the 10 bit values loaded in the ADC0_LIMIT values. The conversion sequence will repeat until either a violation interrupt occurs or the ADC0_EN bit is written to 0. 2. To detect when the average value violates the max/min limits: Set RD_MODE[1:0]) to 01, 10 or 11 and REPEAT to 1. At the end of the multiple sample conversion cycle the ALU will calculate the 12 bit average of the sample values by shifting the AVG[15:0] register (shift right 2 if 16 samples, shift right 3 if 32 samples and shift right 4 if 64 samples) . The shifted 12-bit average value is then compared to the value programmed in registers ADC0_LIMIT. DETAILED DESCRIPTION 84 Submit Documentation Feedback |
Аналогичный номер детали - TPS658620ZQZT |
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Аналогичное описание - TPS658620ZQZT |
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