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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TPS658620ZQZT датащи(PDF) 79 Page - Texas Instruments |
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TPS658620ZQZT датащи(HTML) 79 Page - Texas Instruments |
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79 / 104 page  3.62.3 CONFIGURING THE ADC CONVERSION CYCLE 3.62.3.1 NUMBER OF SAMPLES AND ADC INPUT SETUP TPS658620 Advanced Power Management Unit www.ti.com SLVS993 – OCTOBER 2009 The timing engine has an internal ALU that stores the converted data in an internal accumulator, executing mathematical operations with the stored data. A conversion cycle ends when the accumulator data is transferred to the TPS658620 ADC RAM data registers. When the conversion cycle is completed, an interrupt request corresponding to indicate end of conversion operation is generated. The interrupt controller subsystem will set the ACK_ADC (bit B1, register 0xB6) to indicate the source of the interrupt was the ADC subsystem. Additional information is available in the ADC0_INT register (0x9A). Register ADC0_SET controls the following parameters for a conversion cycle: conversion start, continuous or fixed-interval sampling mode, number of samples to be taken and channel selection. Setting the ADC0_EN bit to 1 will start the conversion process. While a conversion cycle is being executed (and conversions are being taken) the ADC0_INT register cannot be externally accessed. The ADC engine has a BUSY signal generated by the ADC Digital Control Logic to indicate this condition. If the ADC0_EN bit is cleared to 0 during a conversion, the conversion cycle will continue until the number of samples specified with the RD_MODE bits has been taken so that the SUM (average) value from the accumulator will be valid. The ADC0_EN bit must be set to 0 before a new conversion configuration is set up. Table 3-59. ADC0 Conversion Selection ADC0_SET [Addr 0x61] Default in BOLD Bit B7 B6 B5 B4 B3 B2 B1 B0 Number Bit Name ADC0_EN REPEAT0 RD0_MODE[1] RD0_MODE[0] CHSEL0[3] CHSEL0[2] CHSEL0[1] CHSEL0[0] ADC0 CONVERSION ADC0 REPEAT Function READINGS IN A CONVERSION ADC0 INPUT CHANNEL SELECTION START MODE ENABLE When 0 DISABLED DISABLED SEE ADC READING SETTINGS SEE ADC CHANNEL SELECT SETTINGS When 1 ENABLED ENABLED Table 3-60. ADC Readings Setting (Default in BOLD) NUMBER OF RD0_MODE[1] RD0_MODE[0] READINGS 0 0 1 0 1 16 1 0 32 1 1 64 Table 3-61. ADC Channel Select Settings (Default in BOLD) CHSELn[3:0] CHANNEL CHSELn[3:0] CHANNEL 0000 CH1 1000 CH9 0001 CH2 1001 CH10 0010 CH3 1010 CH11 0011 CH4 1011 AGND 0100 CH5 1100 AGND 0101 CH6 1101 AGND 0110 CH7 1110 AGND 0111 CH8 1111 AGND Submit Documentation Feedback DETAILED DESCRIPTION 79 |
Аналогичный номер детали - TPS658620ZQZT |
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Аналогичное описание - TPS658620ZQZT |
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