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TPS658620ZQZT датащи(PDF) 78 Page - Texas Instruments

номер детали TPS658620ZQZT
подробное описание детали  Advanced Power Management Unit
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3.62.1 ADC EXTERNAL INPUT PINS – BIAS CURRENT SETTINGS
3.62.2 ADC TIMING ENGINE OVERVIEW
TPS658620
Advanced Power Management Unit
SLVS993 – OCTOBER 2009
www.ti.com
A simplified block diagram for the ADC analog section is show in Figure 3-22.
Figure 3-22. Simplified ADC Block
The external pins ANLG1, ANLG2 and ANLG3 may be biased using internal pull-up current sources, with
current source value set by register ADCANLG. The current sources are turned OFF when the ADC
reference is disabled.
Table 3-57. ADC Input Bias Selection
ADCANLG [Addr 0x60]
Default to 0
Bit Name
ANLG2FLT
ANLG3FLT
IANLG3[1]
IANLG3[0]
IANLG2[1]
IANLG2[0]
IANLG1[1]
IANLG1[0]
Function
SPARE
SPARE
ANLG3 BIAS CURRENT SOURCE
ANLG2 BIAS CURRENT SOURCE
ANLG1 BIAS CURRENT SOURCE
Table 3-58. ANLG3/2/1 Current Source Settings
IANLG[1]
IANLG[0]
Current (
µA)
0
0
0
0
1
3
1
0
10
1
1
50
The COMP pin has no internal pull-up current source.
The ADC timing engine can be configured to perform either one reading, a single-trigger multiple set of
readings, or to operate continuously until high or low limits are violated on any channel.
A conversion cycle includes the following steps:
1. Program the timing engine mode (single sample, multiple sample, etc.) and triggers
2. Enable the internal ADC reference and conversion start delay
3. Select the channel to be used as the SAR input and start the conversion cycle
DETAILED DESCRIPTION
78
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